1. Field of the Invention
The present invention relates to a semiconductor device having a capacitor structure sandwiching a ferroelectric film between a lower electrode and an upper electrode, and to its manufacturing method. In particular, it is preferably applied to a semiconductor device having a ferroelectric capacitor structure in which the dielectric film is a ferroelectric film having ferroelectric characteristics.
2. Description of the Related Art
Recently, development is proceeded with a ferroelectric memory (FeRAM) holding information in a ferroelectric capacitor structure utilizing polarization inversion of a ferroelectric substance. The ferroelectric memory is superior to a flash memory and an EEPROM in low power consumption, the number of times of rewriting and speed of rewriting, and used for such applications as IC cards and SIMs. Further, since the ferroelectric memory is a nonvolatile memory that does not lose held information when a power source is switched off and can be expected to realize high integration, high speed driving, high durability and low power consumption, it particularly attracts attention.    [Patent Document 1] Japanese Patent No. 3591497
Recently, miniaturization/high integration of a semiconductor device proceeds more and more, and there also raises similar expectations for a FeRAM. Further, increase in an amount of accumulated charges is also requested for such semiconductor memory as a FeRAM. Thus, for a FeRAM, in order to satisfy such conflicting request as miniaturization/high integration, and increase in an amount of accumulated charges, increasing in an occupying area of a ferroelectric capacitor structure while reducing memory cell size is required.
In view of this, Patent Document 1 discloses such constitution as plural ferroelectric capacitor structures formed in plural 2-layered structures having a common upper or lower electrode in column direction. However, since the technique of Patent Document 1 has a common upper or lower electrode as described above, it is restricted to a special constitution in which 1 selection transistor is disposed for plural ferroelectric capacitor structures in column direction. In the constitution, carrying out sufficient integration of a memory cell is difficult.